Read channel devices serve as interfaces between a hard disk on which digital information is stored and external devices which receive and process the digital information in various applications. Digital data may be encoded in a suitable format and stored on a hard disk. During retrieval, this stored data must be decoded and converted to a format compatible with hard disk drives that will process the data.
FIG. 1 illustrates a conventional system for reading out data stored on a hard disk. Digital data encoded and stored on disk 11 is read out as a serial data bit stream. The data is filtered and amplified by filter/amplifier 12 and sampled by digital signal processor 13. A Viterbi sequence detector 14 produces the maximum likelihood estimate of the transmitted sequence and interleaves the data into two serial bit streams. The data is then input to the read channel device 15. Read channel device 15 receives 2-bit interleaved data and outputs the data in parallel, byte-wide form. Read channel device 15 is shown in more detail in FIG. 2.
Referring to FIG. 2, clock generator 23 generates a clock signal running at the code rate, or the frequency at which data is read out of the hard disk 11, typically 297.5 MHz. A divide-by-17 clock is then derived from the clock signal by successively frequency dividing the clock signal. The divide-by-17 clock is input to the framing circuit 21 to synchronize the serial to parallel data conversion, as will now be explained.
Framing circuit 21 receives two interleaved serial data streams read out from disk 11 and converts the serial data to 17-bit parallel data in accordance with the 16/17 Run Length Limited (RLL) code format for the read channel device. This is accomplished by "grabbing" 17 bits of serial data every 17 cycles of the code rate clock (every transition of the divide-by-17 clock) from a shift register. FIG. 3 illustrates the interleaved serial data organized into 17-bit parallel data blocks.
Referring to FIG. 3, note that the serial data is interleaved into two bit streams, denoted as even and odd. For example, serial bit 0 (the first bit read out from the hard disk) enters the even bit stream, serial bit 1 enters the odd bit stream, serial bit 2 enters the even bit stream, and so on. Framing circuit 21 "grabs" the first 17 data bits (bits 0-16) from the two serial data streams and groups the 17 bits into a parallel data word. Next, the framing circuit grabs the next 17 bits (bits 17-33) in a similar fashion to form the next parallel data word, and the data conversion continues in this fashion.
The framed 17-bit parallel data is then input to decoder 22, shown in FIG. 2. Using information stored in a timing bit, decoder 22 converts the incoming 17-bit data into 16 bit parallel data words. The 16-bit buffer 24 organizes the data into two standard 8-bit bytes. Test circuit 25 performs a test on the readout data. The NRZ circuit 26 derandomizes the data sequence and outputs 8-bit bytes to the external world.
The above-described decoding scheme suffers from several drawbacks relating to its operation at the code rate. First, power dissipation is high while operating at the code rate. Second, the generation of a divide-by-17 clock requires the use of a 6-stage state machine, thereby increasing implementation size. The higher frequency clock also places requirements on the timing logic and thus creates a limitation on the maximum speed of the read data path.
What is desired is a serial to parallel conversion interface in the read path of a read channel device that is easily implemented, operates efficiently at increased speed, and that consumes a minimum amount of power.